Signal Integrity Validation Engineer

工作内容

UST is a leading provider of IT and Engineering Services and Solutions for Global 500 companies.

Roles & Responsibility:

This SI Validation Engineer will conduct simulation service for Data center customer for their board design check. The work is including Channel Check Tool and OOG design review. Will be responsible for simulation post data process, report wrap up for customers, Workstation maintenance, Software upgrade, scripting development and work with 3rd party vendor for SI tool enhancement. Needs to possess the following skill to carry out the project tasks:

1. Familiar with Cadence Power SI, Sigrity, Speed 2000, Power DC simulation software and tool manipulation.

2. Familiar with Python Language and experienced in programing c.

3. Good reading and writing in English.

4. Need to manipulate tools to conduct simulations including CCT for customer’s board design.

5. 3rd party tool maintenance - Cadence Power SI, Speed 2000, and workstation maintenance.

6. Software script development for Report Post analysis.

The candidate is adept in:

a) Signal Integrity

b) CCT (Speed2K)

c) FD-CCT (PowerSI, SystemSI, FastCCT)

d) Result post process (Python)