Chip Package Interaction (CPI) Engineer, Senior to Staff

工作内容

Company:Qualcomm Semiconductor Limited

Job Area:Engineering Group, Engineering Group > ASICS Engineering

Job Overview:
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

Job Overview

The CPI engineer will be a key member of Taiwan chip package interaction (CPI) and bumping team supporting technology development, new product introduction (NPI) and high volume production (HVM) across various silicon technology nodes, foundries, bumping lines and assembly houses.
The job includes product and test vehicle passivation, redistribution layer (RDL) and bump mask tape out and process set up; test vehicle and product NPI characterization and ramp up data collection; metrology matching and machine fan out; continuous process improvement, HVM issue containment, root cause and resolution.
The candidate is expected to interact closely with foundry backend interconnect, passivation and bumping teams, OSATs bumping and assembly teams, and internal package design, process, quality, test and product development teams to deliver best-in-class design for manufacturability (DFM) on silicon and package interconnect, bump technology, NPI and production execution for Qualcomm’s products.

Minimum Qualifications

Skill/Knowledge: Fundamental understanding of silicon backend interconnect, low K and ELK dielectrics, passivation, RDL, bump, packaging, material and equipment. Strong technical skills in process, material and equipment characterization, failure analysis and FMEA. Strong technical skills in DOE design and statistical data analysis. Working knowledge of silicon mask design and tape out, and package layout.
Minimum of 5 years of hands on working experience on silicon interconnect process, bumping and / or RDL process, new technology qualification and production.
Good analytical and project management skills. Excellent verbal and written communication skills. Highly motivated and committed to success of the individual and the team.
Able to work flexible hours. Occasional domestic/international travels needed.

Preferred Qualifications

Hands on working experience at foundry, bumping line and / or assembly house. Hands-on experience in leading projects and OSATs management in silicon interconnect, bumping, packaging for advanced silicon and package technologies. Additional experience in flip chip package, wafer level package, fan out package and module is a plus.

Keywords
Chip Package Interaction, Interconnect, Low K, Cu pillar Bump, Passivation, Flip Chip, Wafer Level Package, Module

Educational Requirements

M.S. or Ph.D. Materials Science, Mechanical Engineering, Chemical Engineering or equivalent

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport

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