Position: Entry level

Job type: Full-time

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Job content

  • Responsible for analog IP, standard cell, IO layout or Auto Place & Route.
  • DRC/LVS rules fixes.
Responsibilities
  • Responsible for analog IP, standard cell, IO layout or Auto Place & Route.
  • DRC/LVS rules fixes.
Experience

1.3年以上相關工作經驗 ,具備先進製程經驗者佳(16/10/7/5奈米) .
  • 電機相關科系畢
  • Interested in digital or analog layout.
Education

大學以上學歷
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Deadline: 20-12-2024

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