Physical Design Engineer

☞ Sintegra Inc.

Vue: 113

Jour de mise à jour: 05-11-2024

Localisation: New Taipei City

Catégorie: Haute technologie Mécanique / Technique Electrique / Electronique IT - Logiciel

Industrie: Semiconductor Manufacturing

Niveau: Mid-Senior level

Type d’emploi: Full-time

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le contenu du travail

Looking for Block Level Physical Design/ Verification for a 3nm/5nm.

The candidate will be executing P&R tools on a high speed digital semi-custom layout

  • Candidate will assist the DE Leads in executing structural design including Synthesis runs, P&R, APR, Performance Verification involving static timing analysis, FEV and layout verification. Required Skills: ASIC and SoC design experience, Physical design CAD flows and Design convergence. Includes synthesis, APR, STA, LVS and debug.
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Date limite: 20-12-2024

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