Silicon Engineer, Platform IP

工作内容

Google welcomes people with disabilities.

Minimum qualifications:

• Bachelor’s degree in Computer Science, Electrical Engineering, or equivalent practical experience.
• Experience in ASIC architecture, computer architecture, or digital design.
• Experience with scripting or Verilog/SystemVerilog
  
  

Preferred qualifications:

• Master’s degree or PhD in Computer Science, Electrical Engineering or related field.
• 3 years of experience in RTL design, design flow, or SoC integration.
• Experience in low-power design or integration, implementing or validating RTL design.
• Proficient with a scripting language, and excellent C/C++ programming and software design skills.
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Participate in evaluation of future ASIC designs and general architecture and micro-architecture.
• Create tools/scripts to automate RTL generation.
• Perform RTL design and simulation using Verilog/SystemVerilog.
• Work with Design Verification Engineers on the verification.
• Work with multi-site teams in architecture/micro-architecture planning, RTL design, or verification.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .