IC Packaging Signal and Power Integrity Engineer

工作内容

Google welcomes people with disabilities.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• Experience in signal and power integrity simulation of system boards, including ASIC/chipset, DDR memory, and other high-speed communication interfaces.
• Experience with power integrity frequency domain and time domain modeling, simulation, optimization, and correlation.
• Experience with industry SI simulation tools and lab
  
  

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering or Computer Engineering with 5 years of work experience in the power integrity and signal integrity field.
• Experience with EDA tools such as Ansys HFSS, Q3D, SIwave, Cadence PowerSI, PowerDC, Allegro, APD, Keysight ADS, and Synopsys Hspice.
• Experience with lab measurement, validation, and correlation on package, die, and PCB level.
• Knowledge of on-chip power analysis flow (e.g. PTPX), SoC physical design (e.g. floor plan).
• Expertise on PDN simulation, LPDDR, and High speed IO (UFS, MIPI, PCIE, USB, etc.) simulation.
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf core components, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As an IC Packaging Signal and Power Integrity Engineer, you design and build the components that are the heart of the world’s largest and most efficient and powerful device. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the future mobile devices affecting millions of Google users.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Provide package design feasibility study, technology selection, design optimization (stackup, ballmap, decaps, and layout).
• Conduct model extraction, frequency domain and time domain simulation for core power and LPDDR, High Speed IO interfaces (MIPI C/D-PHY, UFS, PCIE, USB2, USB3, DP, etc.).
• Provide SI/PI methodology development, system level design guidelines generation for SOC power and peripheral IOs.
• Perform lab validation, silicon to spice correlation study, current profile measurement, and root cause debugging.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .