Digital Design Manager

工作内容

Andes Deep Learning Accelerator (AnDLA) is a highly efficient and cost-sensitive AI solution for edge devices and endpoints. AnDLA features hardwired processing units for matrix multiplication, convolution, pooling functions, and more in the future.

Your team designs and builds the AnDLA softcore IP. You lead your team from micro-architecture, design, verification, and documentation. You collaborate with SW engineers to optimize the programming sequence from the scheduling perspective. In this role, you help grow and manage a growing deep learning R&D team.

Responsibilities

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AnDLA design lead.

• Define the AnDLA architecture as well as the system architecture with AndesCore processors for deep learning applications.
• Explore various trade-offs of the AnDLA design in terms of performance, power, energy, and area.
• Work with SW engineers to optimize scheduling results.
• Work with AI compiler engineers to optimize compilation results.

Minimum qualifications

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• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• Experience in logic design, and functional and Power Performance Area (PPA) closure.
• Experience with deep learning accelerator (DLA) hardware design.
• Experience with digital design & verification - from IP specification through IP sign-off.
• 6 years of experience in digital design.

Preferred qualifications

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• Knowledge of CPU architecture.
• Knowledge of modeling development.
• Experience with application-specific instruction set processor (ASIP) design or co-processor design.
• Experience with hardware/software co-design and heterogeneous computing.
• Experience with memory subsystem architecture for high-performance design.
• Experience optimizing/architecting software/hardware solutions for deep learning, image/video/packet processing, power and performance analysis.