Staff Engineer, Digital IC Design

Job content

About MarvellAt Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The OpportunityCentral Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.Job ResponsibilitiesASIC design engineer responsible for post RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation and ECOs.The responsibilities include but not limited to.

• Improve the design methodology and flow.
• Synthesis, timing closure and DFT support for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
• Collaborate with Analog/Digital design teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
• Provide the support to the product teams, for both pre and post silicon

RequirementsMaster’s degree and/or PhD in EE, CS or related fields and 3+ years of experience.Good personal communication skills and team working spirit.Hardworking and motivated to be part of a highly competent design team.Must have good post-RTL experience including synthesis, timing analysis and physical design. Able to perform custom placement and routing for mixed-signal designs. Flexible to move between all post-RTL design activities as required. Good understanding of block and top-level physical timing closure.Must Be Proficient In The Following Skills

• Logic or physical synthesis using Synopsys or Cadence tools
• DFT generation and verification
• Static timing analysis using Primetime
• Physical design for 28nm and beyond
• Strong Perl and Tcl scripting skill

Highly Desirable Skills

• Low power design
• Circuit level or custom design experience
• Floorplanning, clock-tree synthesis and power planning/analysis
• Signal integrity and physical verification

The PerksWith competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We’ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.Your FutureMarvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.