Silicon Physical Design Engineer, Mixed Signal

Job content

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Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or Computer Science, or equivalent practical experience with 5 years of experience in physical design
• Experience with synthesis tools/flows working on Verilog or System Verilog designs
• Experience in one or more scripting languages (e.g., Tcl, Python, etc.)
  
  

Preferred qualifications:

• Experience with low-power design techniques such as multiple power domains, power switches, level shifting, isolation, and dynamic voltage/frequency scaling using UPF
• Experience with design-for-test flows and methodology, including insertion, coverage analysis and pattern generation
• Experience with Analog and/or Mixed Signal (AMS / DMS) design integration
• Experience working with highly scaled Complementary Metal Oxide Semiconductor (CMOS) processes (e.g. FinFET)
• Understanding of the full suite of physical design tools (PnR / APR, STA, EMIR, DRC, etc) to drive a block to timing closure and final signoff
• Knowledge of version control systems such as Git
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Generate high quality synthesis results for one or more digital blocks, working closely with front end designers and back end PD integration engineers
• Validate physical design inputs (RTL, timing constraints, low power descriptions, etc) and suggest improvements when issues arise
• Assist in DFT insertion for various block-level designs
• Optimize designs based on key metrics, including power, area, and performance trade-off analyses
• Apply engineering practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .