Signal and Power Integrity Engineer, Pixel

Job content

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Minimum qualifications:

• Bachelor’s degree in Electrical Engineering with a focus on electromagnetic, transmission line, and circuit design, or equivalent practical experience.
• Experience in signal and power integrity modeling and simulation on high-speed interfaces in frequency and time domain.
• Experience with one of electromagnetic/simulation tools (e.g., HFSS, SiWave, PowerSI, Clarity, Hspice, Spectre, finesim, ADS).
• Experience with lab voltage and signal measurement.
  
  

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering.
• 2 years of experience in power integrity and signal integrity field.
• Experience with PDN modeling and simulation.
• Experience with LPDDR and high-speed IO modeling and simulation (e.g., UFS, MIPI, PCIE, USB, etc.).
• Experience with EDA tools such as Ansys HFSS, Q3D, SiWave, Cadence PowerSI, Clarity, PowerDC, Allegro, APD, Spectre, Keysight ADS, and Synopsys Hspice.
• Knowledge of on-chip power analysis flow (e.g., PTPX, Redhawk, Voltus), SoC physical design (e.g., floor plan).
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Participate in package design feasibility study, technology selection, design optimization (e.g., stackup, ballmap, decaps, and layout), model extraction, frequency and time domain power and signal integrity simulation.
• Manage model extraction, frequency domain and time domain simulation for core power and LPDDR, high-speed IO interfaces (e.g., MIPI, UFS, PCIE, USB2, USB3, DP etc).
• Develop SI/PI methodology and generate system level design guidelines for SoC power and peripheral IOs.
• Provide system level design guidelines for SoC power and peripheral IOs.
• Perform lab design validation, correlation study and root cause debugging.
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .