Senior Digital Verification Engineer

Job content

https://jobs.renesas.com/job/Zhubei-Senior-Digital-Verification-Engineer/860003401/

Working as a Senior Digital Verification Engineer based in Zhubei, you will:

• Define test bench infrastructure using SystemVerilog, UVM and/or Formal.
• Responsible for complete digital level verification.
• Modeling of analog functions in SystemVerilog is a plus.
• Responsible for complete chip level verification of mixed signal IC.
• Work closely with design team to architect a new design verification environment and produce high quality verification closure.
• Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.

We are looking for:

• 3+ years of experience in ASIC/IC verification at block level and/or top level testbenches.
• Experience in UVM based verification flow, constrained-random approach and coverage driven DV.
• Good understanding of OOP concepts
• Familiar with scripting language like Makefile, Perl, Tcl or Python.
• Experience in SimVision or Verdi debug skills.
• Experience in Assertion and formal verification (Jasper, 0-in, IFV, Model checking) is a plus.