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Senior Digital Design Verification Engineer
View: 206
Update day: 05-11-2024
Location: Taipei City Taitung County
Category: High Technology Mechanical / Technical Electrical / Electronics IT - Software
Industry: Electrical Electronic Manufacturing Computer Hardware Semiconductors
Position: Associate
Job type: Full-time
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Job content
We’re looking for a Senior Digital Design Verification Engineer.As a Senior Mixed Signal Digital Design Verification engineer at NVIDIA, you’ll verify the design and implementation of our cutting edge SerDes IPs. This ground breaking technology will enable and accelerate gaming, artificial intelligence, deep learning, and autonomous driving. We have put together a world-class team that delivers IPs that will be consumed by standard as well as industry-leading proprietary high-speed protocols.
What You’ll Be Doing
- Responsible for verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.
- Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
- You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
- Write and execute test plan and thoroughly verify a design in a product shipment focused / compressed schedule.
- Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
- Bachelors or Masters Degree in Electrical Engineering or Computer Science or Computer Engineering or equivalent experience.
- At least 5 years of relevant experience.
- Background in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog a must.
- Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.
- Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
- Expertise in bus or interconnect protocols (e.g. PCI Express, USB, SATA) a big plus.
- Background in verifying complex SerDes system, understanding mixed-signal designs, and have experience in modeling of analog circuits a big plus.
- Perl, Python, C/C++ programming language experience.
- Good debugging and analytical skills.
- Great communication skills & dream to work as a great teammate.
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Deadline: 20-12-2024
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