Principal Engineer, Mixed Signal Circuit Design

Conteúdo do emprego

The successful candidate shall lead the design efforts of high-speed low-noise clocking circuity, including the fractional-N phase locked loops and the clock distribution networks.

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity, and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users.

If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!

The high-quality clocking circuitry is the backbone of the high-speed mixed-signal IPs under development here in Infinera. You will have the great chance to demonstrate your creativity and superior technical competency by leading the design efforts to help Infinera hold the market leadership. We together will revolutionize the era of efficient high-speed transmission.

Essential Functions and Key Responsibilities:

• Design, simulate, and verify the high frequency fractional-N PLLs.
• Architect, model, and simulation the noise accumulation and the skew of the clock distribution trees.
• Model, optimize, and measure the phase noise and jitter performance, and the skew of the whole clocking networks.
• Design and implement the high-frequency / low-noise VCOs.
• Collaborate and/or supervise other team members for system design implementation, layout floor planning, and system level modeling.

Mandatory Knowledge/Skills/Abilities:

• Have good tracking records in designing low phase noise LC-VCO based PLLs to production.
• Abundant knowledge in the design trade-offs among different VCO topologies for MM-Wave applications, including but not limited to LC-VCO, TWO, SWO, etc.
• Hands-on in designing the clock distribution network in Cadence environment.
• Good at modeling the phase noise and spurs of the frac-N PLLs.
• Possess extensive experience in designing and implementing the high frequency VCOs and clock trees with EMX tools.
• Have a decent understanding in CMOS analog / mixed signal design overall.

Preferred Knowledge/Skill/Abilities:

• Good at supervising testing activities.
• Fluent in verbal and written communications.
• Independently resolves issues and conquer design challenges.
• Self-motivated and detail oriented.
• Has good interpersonal skills.

Education and Experience Requirements:

• M.S. in E.E. with 10+ years’ experience, or Ph.D. in E.E. with 6+ years’ experience