Senior Principal Package Design Engineer

작업 내용

Job Description

• Lead imager package product design activities including: schematic and package netlist definition; package circuit layout; package simulations; package design review and approval; and package product performance verification.
• Provide direct design support for imager package product designs including wire bond BGA, MCP (multichip package) and WLCSP (wafer level chip scale package).
• Work directly with Product Design, Design Integration, Product Engineering, Test Engineering, Applications Engineering, Hardware Development, Marketing, Packaging R&D, Packaging NPD, Purchasing, OSAT’s, and key package material suppliers.

Qualifications

• Bachelor or Master degree in Electrical Engineering, Mechanical Engineering, or Engineering related.
• 8+ years experience in package and/or hardware system design, assembly process engineering, and new product development.
• Package/PCB layout experience using Cadence APD/SIP required.
• Signal/Power/Ground integrity experience and familiarity with simulation tools such as Cadence Sigrity Package Assessment, ANSYS Q3D, and ANSYS HFSS.
• Mechanical design experience using AutoCad and Solid Works.
• Solid understanding of packaging assembly process and material properties.
• Experience with thermal and mechanical stress simulation using finite element analysis.
• Strong project management and problem solving skills required.
• Able to work independently and interact with multinational team members.
• Bilingual in English and Mandarin Chinese.