Principal Digital Verification Engineer

Renesas Electronics

전망: 139

갱신일: 05-11-2024

위치: Zhubei City Hsinchu County

범주: 다른

산업:

직업 종류: Full-time

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작업 내용

https://jobs.renesas.com/job/Zhubei-Principal-Digital-Verification-Engineer/887469401/

Working as a Principal Digital Verification Engineer based in Zhubei, you will:

  • Define test bench infrastructure using SystemVerilog, UVM and/or Formal.
  • Responsible for complete digital level verification.
  • Modeling of analog functions in SystemVerilog is a plus.
  • Responsible for complete chip level verification of mixed signal IC.
  • Work closely with design team to architect a new design verification environment and produce high quality verification closure.
  • Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.

We are looking for:

  • 8+ years of experience in ASIC/IC verification at block level and/or top level testbenches.
  • Experience in UVM based verification flow, constrained-random approach and coverage driven DV.
  • Good understanding of OOP concepts
  • Familiar with scripting language like Makefile, Perl, Tcl or Python.
  • Experience in SimVision or Verdi debug skills.
  • Experience in Assertion and formal verification (Jasper, 0-in, IFV, Model checking) is a plus.
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마감 시간: 20-12-2024

무료 후보 신청 클릭

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동일한 작업

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