Memory Design Manager

작업 내용

l Job Description: 工作內容：

1. Coordinate full-chip timing closure and database integration

協調全晶片時序收斂和資料庫整合

2. Actively involved in silicon debug and validation

積極參與晶片的Debug調試與驗證

3. Planning and organizing design projects, or phases of design projects

負責研發專案的規劃與組織，並追蹤進度以按時完成研發任務

4. Meet aggressive performance, area, power and schedule targets

在專案計畫時間內實現極致的性能、面積、功耗等設計目標

5. Finish other tasks assigned by supervisors

完成領導交辦的其他事項

Ø Bonus(Optional, better if fits） 加分項（非必須，若符合更佳）

1. Defining, negotiating, and reviewing product requirements/specs

負責定義、協商和評估產品需求與規格

l Qualification：其他條件：

1. Master or PhD Degree in Electrical Engineering or Computer Engineering

擁有電子工程專業或電腦工程專業碩士及以上學歷

2. Candidate should have 7+ years of relevant hands-on CMOS design experience in advanced technology nodes

候選人應具有 7年以上先進技術節點CMOS設計實踐相關的經驗

3. Using English as working language

英語可作為工作語言

l Relative experience：相關經驗

1. Custom circuit design flow

熟悉客制化電路設計流程

2. Programming experience in Unix shell, C/C++, Perl, Skill, TCL, or similar

具有Unix shell、C/C++、Perl、Skill、TCL或類似語言程式設計經驗

3. Fluent in usage of associated EDA tools such as Verilog, Spice, Ultrasim, Virtuoso

熟練使用相關的EDA工具，例如Verilog、Spice、Ultrasim、Virtuoso

Ø Bonus(Optional, better if fits） 加分項（非必須，若符合更佳）

1. Deep familiarity with DRAM standards and technology

精通DRAM標準和技術