Memory Design Manager

작업 내용

Job Description: 岗位职责：

1. Coordinate full-chip timing closure and database integration

协调全芯片时序收敛和数据库整合

2. Actively involved in silicon debug and validation

积极参与芯片的Debug调试与验证

3. Planning and organizing design projects, or phases of design projects

负责研发项目的规划与组织，并追踪进度以按时完成研发任务

4. Meet aggressive performance, area, power and schedule targets

在项目计划时间内实现极致的性能、面积、功耗等设计目标

5. Finish other tasks assigned by supervisors

完成领导交办的其他事项

Bonus(Optional, better if fits） 加分项（非必须，若符合更佳）

1. Defining, negotiating, and reviewing product requirements/specs

负责定义、协商和评估产品需求与规格

Qualification：任职资格：

1. Master or PhD Degree in Electrical Engineering or Computer Engineering

拥有电子工程专业或计算机工程专业硕士及以上学历

2. Candidate should have 7+ years of relevant hands-on CMOS design experience in advanced technology nodes

候选人应具有 7年以上先进技术节点CMOS设计实践相关的经验

3. Using English as working language

英语可作为工作语言

Relative experience：相关经验

1. Custom circuit design flow

熟悉客制化电路设计流程

2. Programming experience in Unix shell, C/C++, Perl, Skill, TCL, or similar

具有Unix shell、C/C++、Perl、Skill、TCL或类似语言编程经验

3. Fluent in usage of associated EDA tools such as Verilog, Spice, Ultrasim, Virtuoso

熟练使用相关的EDA工具，例如Verilog、Spice、Ultrasim、Virtuoso

Bonus(Optional, better if fits） 加分项（非必须，若符合更佳）

1. Deep familiarity with DRAM standards and technology

精通DRAM标准和技术