Lead Application Engineer

작업 내용

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Application Engineer(Digital Verification/NC-Verilog/Xcelium/Verisium)Job Discerption

• Support customers migrate verification solution to Xcelium
• Assist customers to solve problems related to low power verification using Xcelium
• In AI-related technologies, support customers integrate Verisium related technology to ensure that the technology can be quickly deployed in the customer’s verification environment
• Work closely with PE and RD team and support for Cadence verification and simulation solution
• Problem solving and help Cadence R&D to enhance the verification tool quality
• Conduct basic and advanced trainings, presentations and demos as necessary

Position Requirements

• Minimum 5 years hands-on expertise on SoC design and verification technique
• Design or Verification experience SoC chip design is required
• Familiar with Verilog/SystemVerilog is a must
• Familiar with one of Python/Perl/TCL scripting language
• Good English Communication
• Advanced Verification Methodology like UVM is a plus

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