Design Verification manager

작업 내용

• Willing to work in a challenging but fun startup environment
• Able to design SoC level verification scheme and plan
• Willing to work with RD/flow development team to build custom verification environment
• Leadership to grow verification engineering team
• Capable of building up various verification environment based upon different user needs and scenarios based upon C, Verilog, SystemVerilog or UVM.
• Familiar with different verification skills, such as signal driven port to port verification, system bus based IP verification, VIP based system level verification and constraint random