Advanced Process Node Foundry Interface Engineer, Silicon

작업 내용

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Minimum qualifications:

• 3 years of experience in advanced CMOS process development in sub-10nm Semiconductor processes
• Experience in trade-off involving product performance/power, yield, and its impact on product PPA and yield ramp
• Experience with Fab process window, Parametric process window, yield impact characterization through DOE, test structure design, and verification
  
  

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Physics, or other related field with emphasis on semiconductor materials and device physics
• Experience with drive foundry in identifying yield detractors, find recipes to improve yield, and demonstrate/validate via DOEs
• Experience in yield analysis, yield pareto, and root cause analysis through diagnostic tools
• Understanding of FINFET/GAA and advanced device architecture
• Understanding of the SPICE modeling and silicon to SPICE correlation
• Understanding of yield analysis tools
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As the Advanced Process Node Foundry Interface Engineer, you will be responsible for driving Complementary Metal–Oxide–Semiconductor (CMOS) foundry partners, tracking design kits, design collaterals development, assess technology risks, and work on test chips. You will support IP, Chip Design, and Implementation teams on planning and performing CMOS scaling, Power Performance Area (PPA) analysis, and producing technology roadmap benchmarks.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Work with foundry partners on optimization of transistor (e.g., Logic/SRAM/IOs) performance/goals on advanced CMOS technology platform, meeting Google product performance and power requirements.
• Work with Google’s internal Design, Product Management, and Power teams to understand the key product indicator optimization window, and find process solutions/trade-offs to meet product needs.
• Understand foundry process integration scheme and design rules for power/performance/area, product yield, and fast manufacturing ramp.
• Lead foundry interactions on device performance/goal, Middle of Line (MOL), BEOL Back End of the Line (BEOL), RC goals, yield, and process window trade-offs.
• Lead model to silicon verification through multiple test vehicles, and help bring products to market with entitlement yield.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .