經營管理類-研發處級主管(封裝模擬)

작업 내용

工作內容

• Responsible for package design simulation and substrate layout including WB, FC, CIS, AiP, TSV and FO.
• More than 7 years experience on thermal, mechanical and electrical simulation for IC packaging.
• Experience on ANSYS, HFSS, Cadence SIP and APD software,
• Experience on validation Lab including Shadow moire, material, thermal and electrical property measurement.
• Excellent 8D problem solving skills and communication skills.
• Lead and manage Simulation and validation Lab.

工作條件