Sr. FPGA /CPLD Engineer (Server & Storage)

仕事内容

JOB SUMMARY

Under the guidance of management, develops new engineering design of a basic to moderate complexity. Gathers design requirements and recommends steps to implement basic to moderate reference design. implementation or design modifications of existing product. Perform and analyze basic to moderate circuit design, referring more complex issues to management or more senior team members. Develop subsystem architecture at the direction of a Sr. Engineer or above.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Work closely with Hardware, BIOS, BMC, and Firmware team for CPLD / FPGA design, validation, and maintenance
• Develop Server / Storage production power on sequence control logic by CPLD / FPGA
• Implement new technology and design concept in CPLD / FPGA
• Design test plan, development specification, and issue tracking

JOB QUALIFICATIONS

KNOWLEDGE REQUIREMENTS

TECHNICAL KNOWLEDGE & SKILLS

• 1~5 years of working experience in CPLD/FPGA development
• Familiar with CPLD / FPGA design and Verilog/VHDL coding
• Experience in I2C, SPI, UART, and SGPIO protocols
• Experience in RTL coding and simulation is a plus
• Building in the area of CPLDs and FPGAs including coding practice, RTL coding standards, using Git, building test benches, etc.

NON-TECHNICAL KNOWLEDGE & SKILLS

• Influence others and share best practices.
• Effectively communicate with good understanding of English.
• Work as part of a global team.

EDUCATION & EXPERIENCE REQUIREMENTS

• Electrical Engineering Degree (BSEE/MSEE or equivalent experience)
• 1+ years experience in CPLD/FPGA design or other key competency
• Or an equivalent combination of education, training or experience.

Domestic and international travel is required (within 1 month)