Sr. FPGA/CPLD Engineer

仕事内容

At Jabil we strive to make ANYTHING POSSIBLE and EVERYTHING BETTER. With over 260,000 diverse, talented and dedicated employees across 100 locations in 30 countries, our vision is to be the most technologically advanced and trusted manufacturing solutions provider. We combine an unmatched breadth and depth of end-market experience, technical and design capabilities, manufacturing know-how, supply chain insights and global product management expertise to enable success for the world’s leading brands. We are driven by a common purpose to make a positive impact for each other, our communities, and the environment.

Build your career with Jabil! We challenge and empower you to make most of your talents, working with outstanding colleagues from diverse backgrounds who share your drive and passion to make Jabil grow!

Job Summary

Under the guidance of management, develops new engineering design of a basic to moderate complexity. Gathers design requirements and recommends steps to implement basic to moderate reference design. implementation or design modifications of existing product. Perform and analyze basic to moderate circuit design, referring more complex issues to management or more senior team members. Develop subsystem architecture at the direction of a Sr. Engineer or above.

Essential Duties And Responsibilities

• Work closely with Hardware, BIOS ,BMC, and Firmware team for CPLD / FPGA design, validation, and maintenance
• Develop Server / Storage production power on sequence control logic by CPLD / FPGA
• Implement new technology and design concept in CPLD / FPGA
• Design test plan, development specification, and issue tracking
  
  

Job Qualifications

KNOWLEDGE REQUIREMENTS

Technical Knowledge & Skills

• 1~5 years of working experience in CPLD/FPGA development
• Familiar with CPLD / FPGA design and Verilog/VHDL coding
• Experience in I2C, SPI, UART, and SGPIO protocols
• Experience in RTL coding and simulation is a plus
• Building in the area of CPLDs and FPGAs including coding practice, RTL coding standards, using Git, building test benches, etc.
  
  

Non-technical Knowledge & Skills

• Influence others and share best practices.
• Effectively communicate with good understanding of English.
• Work as part of a global team.
  
  

Education & Experience Requirements

• Electrical Engineering Degree (BSEE/MSEE or equivalent experience)
• 1+ years experience in CPLD/FPGA design or other key competency
• Or an equivalent combination of education, training or experience.
  
  

Domestic and international travel is required (within 1 month)

Jabil, including its subsidiaries, is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, national origin, sex, sexual orientation, gender identify, age, disability, genetic information, veteran status, or any other characteristic protected by law. BE AWARE OF FRAUD: When applying for a job at Jabil you will be contacted via correspondence through our official job portal with a jabil.com e-mail address; direct phone call from a member of the Jabil team; or direct e-mail with a jabil.com e-mail address. Jabil does not request payments for interviews or at any other point during the hiring process. Jabil will not ask for your personal identifying information such as a social security number, birth certificate, financial institution, driver’s license number or passport information over the phone or via e-mail. If you believe you are a victim of identity theft, contact your local police department. Any scam job listings should be reported to whatever website it was posted in.