Silicon Reliability Engineer, Integrated Circuit

仕事内容

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Minimum qualifications:

• Bachelor’s degree in Electrical or Mechanical Engineering, or equivalent practical experience.
• 6 years of experience in applying Design for Reliability techniques.
• Experience in reliability physics, statistical analysis (JMP, Weibull), lifetime, and FIT projection of semiconductor ICs.
  
  

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Material Science, Mechanical Engineering, Physics, or a related field.
• 6 years of experience in design, development, reliability qualification, and production of advanced IC packages including FOWLP, FOPLP, WLCSP, PoP, 2.5D, and 3D.
• Experience in semiconductor failure analysis tools such as SEM, TEM, FIB, EDX, CSAM, Nanoprobe, CT Scan, X-Ray, and Decapping.
• Background in package and board-level reliability (TCoB, Mechanical Shock, Shadow Moire, and MLB strain) testing.
• Background in reliability physics, statistical analysis (Design Expert, JMP, Weibull), lifetime, FIT, failure rate projection of semiconductor devices and components.
  
  

About The Job

As part of the Silicon Reliability Group, you will be responsible for the design, development, and reliability assessment of the high performance Integrated Circuit (IC) packages used in Consumer Hardware systems. The work will include Silicon IC package technology development and its reliability, board-level reliability tests, reliability lifetime projections, package materials and failure analysis, and execution of corrective actions to meet the IC performance specs. In this role, you will study the reliability and manufacturability of new packages with underfill materials used in manufacturing. You will work with cross-functional teams including chip design, IC package design, product engineering, manufacturing, and suppliers to ensure that IC packaging solutions can meet the Consumer Hardware spec requirements.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user’s interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people’s lives better through technology.

Responsibilities

• Lead the reliability of advanced IC package technology (FOWLP, FOPLP, WLCSP, PoP, 2.5D, and 3D) for SOCs designed in 5nm Finfet possess technology and beyond.
• Conduct IC package board-level reliability tests, such as Temperature Cycling on Board (TCoB), mechanical shock, warpage, and board-level strain to project lifetime and generate physical model parameters for the Finite Element Analysis (FEA).
• Conduct failure analysis of solder balls, bumps, package substrate, RDL, and IMC at the package/board interface to determine the root cause of failures in reliability testing.
• Study the manufacturing robustness and reliability of new materials such as underfill materials on advanced SOC packages.
• Use statistical reliability analysis tools, such as JMP and Weibull, to model the experimental test data and project lifetime of the packages under field applications.
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .