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Platform Manager, External Platform Planning
見る: 123
更新日: 05-11-2024
場所: Hsinchu City
レベル: Mid-Senior level
ジョブタイプ: Full-time
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仕事内容
Job DescriptionThis is a senior technical leadership position within the Foundry Technology and Engineering (FTE) organization in Global External Manufacturing and Sourcing (GEMS). The successful candidate will be part of planning team who drives a horizontal, multi-foundry ecosystem approach to process, packaging, and IP technology definition and enablement. The key objective is to leverage best-in-class foundry, packaging/assembly/test (PAT) and IP ecosystem capabilities to complement internal offerings as a competitive advantage to power Intel’s portfolio of products. To achieve this objective, the candidate will collaborate with internal and external stakeholders to shape the overall technology/PAT/IP roadmap, identify product and platform readiness gaps/options, and drive risk management recommendations to address Intel product requirements. The extensive scope includes: process, packaging, TFM and IP testchip definition/requirements and platform execution planning.Responsibilities Will Include, But Not Be Limited To- Partner with internal product, external foundry (TSMC, Samsung, others), PAT suppliers, TFM/IP suppliers and supply chain teams to understand overall product requirements, including PPAC targets, timelines, and testchips.
- Partner with external foundry and PAT suppliers (internal and external) to understand/address technology and cost/capacity planning.
- Drive the platform readiness plan (especially testchips) to mitigate risks of process/PDK, TFM, and IP designs with the overarching goal of bringing together the right components to allow Intel to deliver industry leading products across segments of interest.
- Leverage and augment available industry competitive data to help guide the co-optimization effort such that we establish leadership foundry/PAT portfolio.
- Influence the ecosystem function and organization within CPG to support current and future generations of process nodes under definition, including strategy/sourcing, pre/post-silicon review, PDK/collateral compliance/QA infrastructure, testchip/validation plan, etc.
- Some amount of travel, when safe and necessary, to meet customers and suppliers may be required.
- Deep knowledge of the latest (7nm or newer) silicon manufacturing technologies development capabilities, device physics/models and scaling.
- Deep knowledge and experience in process feature, tool, logic and memory circuit optimization for low-power and high-speed VLSI.
- Deep knowledge of process, packaging and TFM/IP customer requirements, portfolio/supplier management, competitive benchmarking and industry trends.
- Knowledge of industry standard CAD tools/flows for digital and/or analog design. Specific experience with Cadence Virtuoso and Spectre/Hspice is a plus.
- Demonstrate capacity to address complex problems algorithmically.
- Very strong communication skills with the ability to take complex topics and concepts and synthesize them as appropriate for effective consumption by a wide range of individuals (engineering level to executive level).
In certain circumstances the work model may change to accommodate business needs.
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締切: 20-12-2024
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