Physical Design Engineer, Low Power SoC

仕事内容

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Minimum qualifications:

• Bachelor’s degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
• 3 years of experience in ASIC physical design implementation and verification (e.g., synthesis, place and route, static timing analysis, formal verification, physical verification, engineering change orders, and power analysis).
  
  

Preferred qualifications:

• Experience with leading one or more aspects of physical design.
• Experience in IP integration (e.g., memories, IOs, embedded processors, DDR, networking fabrics, and Analog IP).
• Experience in extraction of design parameters, QOR metrics, and analyzing trends.
• Working knowledge of semiconductor device physics and transistor characteristics.
• Ability to write scripts in Python, Tcl, or Perl.
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Perform block level physical implementation steps including synthesis, floor-planning, place and route, power/clock distribution, congestion analysis, timing closure, EM/IR analysis, and formal verification.
• Work with logic designers to drive architectural feasibility studies, develop timing, power, and area design goals, and explore RTL/design trade-offs for physical design closure.
• Develop physical design methodologies and automation scripts for various implementation steps.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .