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ASIC Interface Architect
見る: 206
更新日: 05-11-2024
場所: Banqiao District New Taipei City
ジョブタイプ: Full-time
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仕事内容
Google welcomes people with disabilities.Due to the current health crisis related to COVID-19 and the escalating visa/travel restrictions in place, we’re currently unable to extend offers to anyone who cannot work from Taiwan due to lockdown visa/travel restrictions, or other restrictive measures until further notice. Consequently, we will be prioritizing candidates who can start in this location by set date as expected. We’re keeping the situation under review and would adjust our position should the restrictive measures be removed later on.
Minimum qualifications:
- Bachelor’s degree in Computer Science, Electrical Engineering, or equivalent practical experience.
- 5 years of experience.
- Experience with one or more high speed serial interface protocol.
- Master’s degree in Computer Science or Electrical Engineering.
- 8 years of experience.
- Experience in I/O interface architecture and micro-architecture.
- Experience with evaluating, selecting, and configuring third party interface IPs.
- Experience with some of the following interfaces: DisplayPort 1.4, 2.0; HDMI; CSI-2 2.x, 3.y; DSI-2 1.x; SPMI; I3C 1.x / I2C; SPI; UARTs; TDM / I2S / Soundwire; PDMs.
- Expert knowledge with one or more of the following interfaces: PCIe gen3, 4; USB 2, 3.x; UFS 3.x; SD; NVMe.
Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.
As an ASIC Interface Architect, you’ll lead the architectural definition/configuration of the I/O subsystems of ASIC products. You’ll collaborate with Software and Hardware Architects to build a compelling, rich set of interfaces, and justify your decisions with the performance of relevant workloads and use-cases. Utilizing your standards-specific knowledge, you will support the configuration and integration of I/O cores into the overall design, including working with the power, clock, fabric, security, system, and all other related architects.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user’s interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people’s lives better through technology.
Responsibilities
- Define the I/O interface architecture of future ASICs. Author the architecture and micro-architecture specifications.
- Collaborate with company-wide stakeholders like Product Management, System Architecture, and Software Engineering to develop I/O interface roll-up and features.
- Understand device usage scenarios and help drive tradeoffs. Perform performance, power, area (PPA) evaluation of prospective IPs and sub-systems.
- Work closely with design, verification, physical design, and silicon validation teams to ensure the implementation follows the architectural and micro-architectural intent.
- Monitor and contribute to relevant standards bodies. Monitor relevant industry and academic trends.
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締切: 20-12-2024
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