3DIC Design Methodology and Flow Development Engineer

仕事内容

Job Details:

Job Description:

• IFS Customer Design Enablement (CDE) team is a critical team to lead Intel’s design methodology and flow in advanced technology.
• As a role in IFS CDE team, should be familiar with entire 3DIC design flow and qualified to have design flow integration or design flow enablement experience in 3DIC design.
• In this position, the candidate will be responsible for the 3DIC design methodology/flow development especially in the areas of design partition, floorplanning, I/O and Bump/TSV planning, thermal, and flow integration.
• As part of this role, the candidate is expected to work with various cross functional teams and external EDAs to oversee the execution all the way.
• The candidate is capable to run 3DIC flow and responsible to figure out the potential flow issue, create 3DIC EDA enablement SPEC, validate new design flow/methodology.
• In addition to the above, the candidate’s ability to come up with a design solution is a plus.
• The selected candidate for the 3DIC Design Methodology and Flow Development Engineer position will be responsible for but not limited to:
• Strong expertise in any one or multiple of the following areas: Advanced 3DIC design including design partition, floor planning, I/O and Bump/TSV planning, design flow integration, and thermal analysis using commercial EDA tools from vendors such as Synopsys, Cadence, Siemens, etc.
• 3DIC design flow development and EDA tool certification 3DIC Design Service and FAE (Field Application Engineering)
• Design automation Self-motivated and detail-oriented, capable of articulating complex concepts and solutions Demonstrated design experiences to secure supports and working experiences with cross-functional teams in achieving goals
• The ideal candidate should exhibit the following behavioral traits:
• Coordination mindset with a focus on development design methodology and flowSkills with EDA ecosystem partnership collaborations
  

Qualifications:

Minimum Qualifications:

• MS/Ph.D. degree in Electrical Engineering, Computer Science, or a related field of study
• 3+ years experiences in 3DIC design, flow development, and EDA enablement
• Minimum 1+ years’ experience in ASIC (APR) design
• Knowledge in any one or multiple of the following areas: analog IC design, digital IC design, semiconductor manufacturing, assembly, and packaging basics
• Technical background in EDA tools
• Programming skill in one or more: TCL, SKILL, Python
  

Preferred qualifications:

• Experiences with 2/2.5D and/or 3D integration chip design
• Experiences in 2/2.5D and 3D simulation tools and methodology, especially for signal integrity and power integrity
• Experience in ASIC (APR) FE/BE design methodology/flow is a plus
• Evidence of organizational and planning skills for engineering projects
• Good communication and presentation skills to executive project coordination
• Experience working with multiple function teams for EDA ecosystem
  

Job Type:

Experienced Hire

Shift:

Shift 1 (Taiwan)

Primary Location:

Taiwan, Hsinchu

Additional Locations:

Business group:

Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers’ unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel’s secure, resilient and sustainable source of supply.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.