TPU Power Architect

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Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Banqiao District, New Taipei City, Taiwan 220; Xindian District, New Taipei City, Taiwan.Minimum qualifications:

• Bachelor’s degree or equivalent practical experience.
• 8 years of experience in semiconductor design and development with a focus on low power design, implementation, and methodologies.
  
  

Preferred qualifications:

• Master’s degree or PhD in Electronics or Computer Engineering, with an emphasis on computer architecture, performance, or power analysis.
• Experience in peak power management, in-rush current, PDN droop detection and mitigation, clock planning, power aware floorplanning, and compute thermal management.
• Experience with full product delivery cycle such as definition, architecture, design and implementation, testing, productization.
• Understanding of techniques used to manage power delivery and thermal limits in compute IP.
• Understanding of PMICs, power delivery, board-level impedances, etc.
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user’s interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people’s lives better through technology.

Responsibilities

• Drive TPU peak power and voltage droop (Vmin) management and mitigation architectures and strategies.
• Drive both pre-silicon design and post-silicon validation and tuning to optimize power and reduce TPU design margins.
• Own and collaborate with power architect, Power Delivery Network (PDN) team and Power Management Integrated Circuit (PMIC) team to evaluate and characterize TPU related SoC level mitigation specification.
• Optimize TPU user experience tradeoffs in the presence of TPU peak power constraints.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .