ASIC Design Verification Engineer

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Google welcomes people with disabilities.

Due to the current health crisis related to COVID-19 and the escalating visa/travel restrictions in place, we’re currently unable to extend offers to anyone who cannot work from Taiwan due to lockdown visa/travel restrictions, or other restrictive measures until further notice.

Consequently, we will be prioritizing candidates who can start in this location by set date as expected. We’re keeping the situation under review and would adjust our position should the restrictive measures be removed later on.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• Experience verifying digital logic at RTL using SystemVerilog for FPGAs and/or ASICs.
• Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
• Experience creating and using verification components and environments in standard verification methodology.
  
  

Preferred qualifications:

• Master’s or PhD degree in Electrical Engineering or Computer Science.
• 3 years of relevant work experience.
• Experience with image processing, computer vision, and/or machine learning applications.
• Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
• Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
• Experience with verification techniques.
  
  

About The Job

As an ASIC Design Verification Engineer, you will be part of a Research and Development team, and your responsibilities will include building verification components, constrained-random testing, end-to-end system testing, and verification closure.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .