Position: Entry level

Job type: Full-time

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Job content

【Job Description】

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【Others】

工作經歷:不拘

學歷要求:碩士以上

科系要求:電機電子工程相關、資訊工程相關

語文條件:英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等

擅長工具:

  • Spectre or Hspice
  • Verilog-A, Verilog-HDL (nice to have)

工作技能:

  • ADC: SAR, Delta-Sigma, Pipeline
  • Switching power converter: Buck, Boost
  • Voltage regulator: digital or analog LDO
  • Special purpose analog/mixed-mode IC design
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Deadline: 20-12-2024

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