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I/O Circuit Design Engineer (IP)
View: 103
Update day: 05-11-2024
Location: Hsinchu City
Category: Other
Industry: Wireless Services
Job type: Full-time
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Job content
CompanyQualcomm Semiconductor LimitedJob AreaEngineering Group, Engineering Group > ASICS EngineeringGeneral SummaryAs a leading technology innovator, Qualcomm pushes the boundaries of what’s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.This is a design position in the I/O Pad design team working on delivering quality low power I/O IP in state of art CMOS/FinFET technology nodes for Qualcomm’s advanced mobile baseband, Auto, IOE/IOT & consumer products. Join QCT’s IP team in designing and implementing I/Os for Qualcomm’s next generation chipsets. The team is responsible for the complete design lifecycle, from system-level concept to tape out and post-silicon support, of advanced digital and mixed-signal ASIC designs in advanced CMOS/FinFET processes.Responsibilities- Mixed-signal transistor level circuit design for General Purpose I/O (GPIO) and Custom I/Os, including specialty I/O such as eMMC, SDC, I2C, RGMII, LVDS, SLIMBus, RFFE, SPMI
- Soundwire and multi-level voltage I/Os using low voltage transistors. Circuit design & Simulations for I/O circuitry
- Work with layout, packaging and system engineers to meet design specifications.
- Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Proven track record of mixed-signal transistor level circuit design in the field of I/Os.
- Recent experience in I/O designs for wireless devices including Low-Power I/O design.
- Solid understanding of related CMOS and FinFET process technology issue.
- Familiar with I/O design methodology & flow, Calibration, JTAG design requirements, understanding of analog circuitry.
- Familiarity with ASIC flow: Synopsys libraries, LEF, CPF, UPF, Place & Route & understanding of top level verification flow.
- Familiar with Power & Signal Integrity and understanding of signal switching, noise & design issues.
- Experience in Cadence Virtuoso (Layout)
- Experience/skills in the following areas are highly valued: SKILL, PERL & TCL scripting, writing Verilog/VHDL, IBIS modeling, characterization and generating .LIBs.
- Familiarity with package/board constraints is a plus
- Proven successful track record as a team player with an engineering team.
- Excellent communication skills and ability to work across multiple teams in multiple locations.
- Possess accountability and ownership.
- All levels of CMOS & FinFET IC development experience.
- Works independently with minimal supervision.
- Provides supervision/guidance to other team members.
- Decision-making is significant in nature and affects work beyond immediate work group.
- Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.
- Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).
- Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.
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Deadline: 20-12-2024
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