Type d’emploi: Full-time

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le contenu du travail

※ Job Contents:

1. SoC/Subsystem verification :

Job includes IP simulation bring up and testbench promote to subsystem/chip level.

2. SoC/Subsystem design :

Job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, STA and FPGA verification.

※ Requirements:

1. MS or PhD degree in EE, CS, or relevant fields

2. Good at digital IC front-end design flow such as Verilog/VHDL RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA

3. Experience in chip integration or subsystem design

4. Familiar with shell scripts for design automation such as Perl language

5. Familiar with ARM CPU and bus fabric is a plus

6. Familiar with DDR, PCIe or USB is a plus

7. Fluent in English communication is a plus

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Date limite: 20-12-2024

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