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Platform Manager, External Platform Planning
Vue: 117
Jour de mise à jour: 05-11-2024
Localisation: Hsinchu City
Catégorie: Haute technologie Mécanique / Technique Electrique / Electronique IT - Logiciel
Industrie: Semiconductor Manufacturing
Niveau: Mid-Senior level
Type d’emploi: Full-time
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le contenu du travail
Job DescriptionThis is a senior technical leadership position within the Foundry Technology and Engineering (FTE) organization in Global External Manufacturing and Sourcing (GEMS).The successful candidate will be part of planning team who drives a horizontal, multi-foundry ecosystem approach to process, packaging, and IP technology definition and enablement.The key objective is to leverage best-in-class foundry, packaging/assembly/test (PAT) and IP ecosystem capabilities to complement internal offerings as a competitive advantage to power Intel’s portfolio of products. To achieve this objective, the candidate will collaborate with internal and external stakeholders to shape the overall technology/PAT/IP roadmap, identify product and platform readiness gaps/options, and drive risk management recommendations to address Intel product requirements. The extensive scope includes: process, packaging, TFM and IP testchip definition/requirements and platform execution planning.Responsibilities Will Include, But Not Be Limited To- Partner with internal product, external foundry (TSMC, Samsung, others), PAT suppliers, TFM/IP suppliers and supply chain teams to understand overall product requirements, including PPAC targets, timelines, and testchips.
- Partner with external foundry and PAT suppliers (internal and external) to understand/address technology and cost/capacity planning.
- Drive the platform readiness plan (especially testchips) to mitigate risks of process/PDK, TFM, and IP designs with the overarching goal of bringing together the right components to allow Intel to deliver industry leading products across segments of interest.
- Leverage and augment available industry competitive data to help guide the co-optimization effort such that we establish leadership foundry/PAT portfolio. 5. Influence the ecosystem function and organization within CPG to support current and future generations of process nodes under definition, including strategy/sourcing, pre/post-silicon review, PDK/collateral compliance/QA infrastructure, testchip/validation plan, etc.
In certain circumstances the work model may change to accommodate business needs.
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Date limite: 20-12-2024
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MÊMES EMPLOIS
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⏰ 05-12-2024🌏 Hsinchu City
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⏰ 05-12-2024🌏 Hsinchu City
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⏰ 05-12-2024🌏 Hsinchu City
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⏰ 05-12-2024🌏 Hsinchu City
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⏰ 05-12-2024🌏 Hsinchu City
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⏰ 05-12-2024🌏 Hsinchu City
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⏰ 05-12-2024🌏 Hsinchu City
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⏰ 05-12-2024🌏 Hsinchu City
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⏰ 05-12-2024🌏 Hsinchu City