IC Package Design Engineer

le contenu du travail

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Minimum qualifications:

• Master’s degree in Electrical Engineering, Materials Science, or equivalent practical experience.
• 2 years of experience in package design layout, design verification, and tape out.
• Experience in Cadence APD/SIP and relevant toolsets for advanced SoC with high-speed interface designs.
  
  

Preferred qualifications:

• PhD in Electrical Engineering.
• Experience in design methodology for package design.
• Experience in package routing and component placement for our next generation ICs.
• Experience in working with Package Designer Engineers and Package Technologists through out the full product development life-cycle, creating package layouts for package technology development and products.
• Knowledge of IC packaging and layout tools like Cadence, Allegro.
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

In this role, you will work with Package Designer Engineers and Package Technologists throughout the full product development life-cycle, creating package layouts for package technology development, as well as package routing and component placement for our next generation ICs.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Design the layout complex package substrates, using Cadence Allegro Package Designer for various package technologies, sizes, and stackups.
• Ensure package layout quality and completing tapeout checklists. Package substrate layout design and assembly rules from manufacturing point of view and electrical requirement considerations.
• Perform layout test studies of die bump-out, package pin-out arrangements, and package substrate breakout and printed circuit board breakout.
• Generate high-quality design documents for substrate manufacturers and package assembly houses.
• Enhance the package design work, by coming up with initiatives that drive efficiency, and in turn help improve quality/cost/schedule of the package layout work.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .