CPU Physical Design Lead

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This position requires access to equipment, technical data and technology that is highly controlled under the Export Administration Regulations (EAR). Such access is restricted to U.S. persons or those otherwise authorized by the U.S. government.

Minimum qualifications:

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 10 years of experience with ASIC design implementation flows.
• Experience driving execution for physical design implementation with synthesis, Place and Route, and Static Timing Analysis tools.
• Experience in sign-off convergence including Static Timing Analysis, electrical checks, and physical verification.
  
  

Preferred qualifications:

• 5 years of industry experience on high-performance CPUs.
• Experience leading processor physical design teams.
• Experience delivering metric-driven Power Performance Area (PPA) goals.
• Knowledge of CPUs including critical iterations for timing and low-power microarchitecture and implementation techniques for CPUs.
• Proficiency in programming and scripting languages, such as Python, Tcl, and/or Perl.
  
  

About The Job

In this role, you will be leading a physical design team for all market segments. You will collaborate with Physical Design, CAD, Architects,and Logic Designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure. You’ll also work with Verification and Software teams to understand and implement the design requirements for clocking and power management.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Lead a physical design team.
• Drive design implementation for CPUs.
• Manage block and hierarchical physical implementation and QoR (power, timing, area).
• Collaborate with register-transfer level (RTL) design, cross-site Physical Design, and CAD teams on microarchitectural critical items for timing and power convergence.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .