ASIC Digital Design Engineer, Mixed Signal Design

le contenu du travail

Google welcomes people with disabilities.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Xindian District, New Taipei City, Taiwan; Banqiao District, New Taipei City, Taiwan 220.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or Computer Science or equivalent practical experience
• 3 years of experience in digital design
• Experience with physical design tools/flows or interfacing with physical implementation teams, and experience in Verilog or SystemVerilog
  
  

Preferred qualifications:

• Experience with low-power design techniques such as multiple power domains, clock gating, or dynamic voltage/frequency scaling
• Experience with design-for-test flows and methodology
• Experience with Analog and/or Mixed Signal designs
• Experience working with highly scaled Complementary Metal Oxide Semiconductor (CMOS) processes (e.g. FinFET)
• Working knowledge of version control systems such as git
• Proficiency in one or more scripting languages (e.g., Python, Tcl, etc.)
  
  

About The Job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

In this role, you will architect, design, and verify digital logic using Verilog and SystemVerilog. You will interface with physical design teams to ensure efficient and timing-clean physical implementation of digital logic designs. You will engage with cross-functional teams to integrate digital logic with system on a chip subsystems such as compute cores, communication interfaces, and analog/mixed-signal IP. You will work with production and silicon validation teams to support chip bring-up and production tests.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user’s interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people’s lives better through technology.

Responsibilities

• Architect, design, and verify digital logic using Verilog and SystemVerilog.
• Work closely with physical designers to generate high quality physical implementations through synthesis, place-and-route, timing closure, and verification.
• Engage with system architects and sub-system owners to define specifications and chip functions.
• Perform power, area, and performance trade-off analyses of digital designs and architectures.
• Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .