ASIC Design Engineer, Machine Learning

le contenu du travail

Google welcomes people with disabilities.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 5 years of experience with Application Specific Integrated Circuit (ASIC) design.
• Experience in ASIC or Field Programmable Gate Array (FPGA) development with Verilog/SystemVerilog.
  
  

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Computer Science or a related field.
• Knowledge in computer architecture/memory subsystem architecture.
• Knowledge of power/performance/area trade-offs.
• Knowledge of accelerators (e.g., Machine Learning or Graphics Processing Units) or similar designs.
  
  

About the jobOur computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user’s interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people’s lives better through technology.

Responsibilities

• Architect, design, and implement digital logic using Chisel, Verilog, and/or System Verilog.
• Engage with System Architects, Software, and Sub-System owners to define specifications and chip functions. Engage with Verification and Silicon Validation teams to ensure functionality of the design.
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
• Perform power, area, and performance trade-off analyses of digital designs and architectures.
• Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .