SW Engineer - CAD Developer

Contenido de trabajo

We are hiring SW Engineer – CAD Developer in Taiwan. (Taipei/Hsinchu)

Job Description

• We are seeking a highly motivated and detail-oriented SW engineer with expertise in Electronic Design Automation (EDA) tools development to join our company. The role will be focused on automating state-of-the-art verification products that are based on innovative techniques that came from years of research at Stanford University which we are expanding and moving them into an industrial use. You will be responsible for development, validation, deployment, and maintenance of such tools using advanced software engineering practices. This is a great opportunity to join an elite team and learn, contribute, and innovate in an area that is so in need of a big improvement. The individual will also work with customers to integrate the tool in their verification flow
• We offer an attractive and competitive compensation with meaningful equity for the selected candidate. We also support H1B and Green Card applications for our employees
  

Primary Responsibilities

• The responsibilities will be tailored to the candidate’s skills and expertise and will include several of the following, but not be limited to:
• Full-cycle development of EDA tools for pre-Si and post-Si verification
• Implement best software practices (i.e., SOLID principles, Agile practices)
• Work with both internal and external teams/customers
  

Minimum Qualifications

• MS in CS/CE or equivalent degree
• 3+ years of experience
• Strong algorithmic skills and advanced data-structure analysis
• Strong background in C and C++ programming languages
• Work experience with EDA vendors (e.g., Synopsys, Cadence, Mentor)
• Knowledgeable of scripting languages like Tcl, Perl, Python
• Knowledgeable of RTL description languages (e.g., Verilog)
• Experience with revision control methodology/systems such as github
• Good communication, inter-personal and teamwork skills
• Strong desire to learn various skills needed in a start-up environment
  

Preferred Skills

• The ideal candidate will be able to demonstrate the following behaviors:
• Some experience with synthesis of digital designs. In particular, experience with tools such as Synopsys Design Compiler and/or Cadence Genus
• Some experience with SystemVerilog, Verilog and VHDL