Sr. Package Engineer

Contenido de trabajo

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

Responsibilities

The IC packaging Design and NPI engineers at Synaptics provide package design/development and new package introduction support for a very broad product portfolio utilizing a wide variety of packaging technologies. Packaging engineers are also responsible for the thermal/mechanical/electrical design, analysis, and development of electronic packages. They define overall package performance and specifications and realize technology certification through package design, and co-design.

Packaging engineers establish package material, package processes and interface with Quality and Operations Teams to assure material performance to meet package quality, yield and performance. They also provide consultation concerning packaging problems and improvements in the packaging process to assembly vendors and operations teams.

Typically, packaging engineers work closely with package reliability, assembly engineering and mechanical simulation colleagues to devise package assembly DOE plans, coordinate assembly builds, scrutinize package qualification plans, monitor package reliability testing, failure analysis, and modify processes to meet the intended needs of reliable, high-performance packages. Package engineers will also respond to customer/client requests or events as they occur. They develop solutions to problems utilizing formal education and judgment.

Packaging engineers need to make design decisions to create the highest possible component performance and manufacturability while providing the lowest component and system cost. Finally, packaging engineers will also provide guidance to internal business partners and project teams on cost implications of design decisions.

Qualifications

• Bachelor or Masters in Mechanical Engineering, Materials Science & Engineering, Electrical Engineering, Computer Engineering, or Engineering Science
• More than 5 years of package NPI and design experience.
• Represent the packaging team in core team meetings held by business units for new product introduction (NPI) efforts. Good understanding of a robust NPI process.
• Solid record of good interaction with outsourced assembly and test (OSAT) vendors to provide effective oversight of packaging projects during the NPI and ramp to manufacturing (RTM) phase.
• Experienced in silicon-package co-design with cross-function teams and has good communication skills.
• Hands on experience designing and running design of experiments (DoEs) to optimize package performance or improve reliability or yield issues.
• Good understanding of assembly process flows for a broad range of packaging technologies.
• Good knowledge of signal/power integrity and electrical simulation – ability to work closely with Si and system engineering teams to assure that package designs result in robust signal integrity. Special attention on high speed memory and high-speed video interface applications.
• Good understanding of package thermal simulation characters and heat dissipation design
• Deep understanding of component (package) and 2nd level (package to board) reliability and how package designs can be optimized for reliability performance.
• Experience in doing trade-off analysis for cost optimizations
• Experienced in wire bond, Flip-chip, CSP package design
• Familiar in all forms of bumping processes for flip chip interconnect (Cu pillar bumping, plated/printed solder bumping, ubumping etc.)
• Familiar wafer level chip scale packaging (WLCSP) and fan out wafer level packaging (FOWLP) technologies.
• Experienced in Cadence APD/SIP design tool as well as AUTOCAD or other CAD tools.
• Experience with high density interconnect substrate manufacturing, design rules, layout process and material properties to enable best mechanical and electrical performance
• Familiarity with modern surface mount (SMT) equipment and processes and experience optimizing designs for ease of integration at board level with good robustness.
• Self-motivated team player and are result driven in terms of schedule and design quality
• Spoken and written proficiency in both English and Mandarin is a must
• The successful candidate will be comfortable working across multiple time zones and cultures to enable efficient and successful product development efforts and timely product launches.