Sr. DFT Engineer

Contenido de trabajo

A global tier 1 semiconductor group Taiwan branch RD team.

Responsibilities

• DFT planning & implementation for MBIST/SCAN/ATPG/BSCAN...
• Perform STA & timing closure for DFT modes.
• Create DFT test pattern & perform DFT Verilog simulation.
• Co-work with Test Engineers to bring-up testing in ATE.
• SpringTW*This job is agented by Spring Professional Taiwan, The Adecco Group company.
  

Experience

• Familiar with DFT flow development(MBIST/SCAN/ATPG/BSCAN/LBIST).
• Familiar with DFT realted flow and EDA tools(e.g. compiler, TetraMax, Tessent & Test Kompress).
• Familiar with IC design flow(e.g. verilog/RTL/STA/LEC/Simulation flow).
• Proficient in Unix Shell/Tcl/Perl & programming skills.
• 14nm/7nm & million-gate SOC design experience is a plus.

Master degree above with Electrical Engineering major