Tipo de empleo: Full-time

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Contenido de trabajo

We are looking for a senior engineer to be a part of signal integrity team developing high-speed SI link modeling and analysis to achieve high-speed mixed-signal circuit and channel design challenge, such as next-generation GDDR, PCI-Express Gen6, and even 100GbE or beyond. This achievement will have a real impact on product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

In this job, you will be responsible for the development of high-speed link modeling, and DNN application for SI works and nonlinear high-speed mixed-signal circuit modeling. As such below is the list of requirements

What You’ll Be Doing
  • High-speed link modeling work, including linear/nonlinear modeling
  • SI channel model extraction
  • Work with DNN experts for developing applications in SI works
What We Need To See
  • MS/PhD in EE, CS or CE (communication engineering), or w/ a minimum 5 years of experience as a SI engineer, high-speed circuit designer, or telecommunication algorithm/DSP engineer
  • Strong mathematical background
  • Fluency in either C++ or Python
  • Good knowledge of statistics and digital signal processing
  • Understanding of electromagnetics, specifically electromagnetic waves including transmission line theory
  • Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes
  • Background with ANSYS HFSS/Q3D/SIwave/Designer and Synopsis HSPICE, and Keysight ADS
Ways To Stand Out From The Crowd
  • Practical knowledge of Signal Integrity concerns in high speed singled-ended and differential links
  • Previous Link modelling experience, either GDDR, LPDDR, DDR, or SerDes
  • Previous wireless link modeling experience, and will be interested in wireline link that will use advanced DSP technique
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Plazo: 20-12-2024

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