Senior Mixed Signal Design Verification Engineer - Taipei

Contenido de trabajo

• As a key member of our circuit verification team, you will verify the design and implementation of the industry’s leading GPU.

• Responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies.
• You are expected to understand complex mixed-signal CMOS circuits design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Work closely with Multi-functional teams, circuit and logic design, verification, test engineering to accomplish tasks.
  

• Bachelors Degree in EE, CS or CE or equivalent experience.

• At least 2 years of relevant experience or an Advanced Degree with equivalent experience.
• Experience in deep sub-micron process design experience in CMOS Analog / Mixed Signal Circuit Design.
• Background with design and verification tools (Cadence’s IC design environment, analog circuit simulation tools like HSpice, Finesim, XA).
• Experience in crafting test bench environments for component and top level circuit verification.
• Expertise in System Verilog or similar HVL.
• Strong debugging and analytical skills.
• Perl and C/C++ programming language experience desirable.
• Strong communication skills and ability & desire to work as a great teammate are huge plus.