Posición: Mid-Senior level

Tipo de empleo: Full-time

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Contenido de trabajo

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Position Description
  • To provide key technical support in digital IC design signoff product (Tempus/TempusECO/Certus) and design closure methodology demonstration, and sales presentations.
  • To demonstrate strong ability and to be hands-on with signoff timing closure flow.
  • To support key customer engagements on the business increase.
  • Have real design tape-out experience especially for advanced node design.
  • To play a leading role among other team members, while receive little instruction on routine and general assignments.
Position Requirements
  • Master with 8 years working experience or Bachelor with 10+ years’ experience in IC design. (Cadence Tempus experience will be a plus)
  • Understanding of signoff timing closure flow including STA/SOCV and timing/Power ECO methodology. (Experience for Tempus/Innovus will be plus)
  • Good communication in English and Chinese, good confidence and good self-motivation.
  • Be familiar with shell/perl/tcl etc. script language.
We’re doing work that matters. Help us solve what others can’t.
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Plazo: 20-12-2024

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