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DRAM Product Engineer Lead – Global DFT Alignment
Ver: 111
Día de actualización: 05-11-2024
Ubicación: Taichung City
Categoría: Otra
Industria: Appliances Electrical Electronics Manufacturing Computer Hardware Manufacturing Semiconductor Manufacturing
Tipo de empleo: Full-time
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Contenido de trabajo
Our vision is to transform how the world uses information to enrich life for all.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.JR41055 DRAM Product Engineer Lead – Global DFT AlignmentGeneral Responsibilities Of The Position Are The FollowingAs a DRAM Product Engineer Lead working in the Global DFT Alignment team, you will lead a team of engineers to collaborate with Global Design For Test (DFT), Test Development, Silicon Strategy teams across DRAM & Emerging Memory portfolio to streamline cross-portfolio review of test coverage and promote business process to collectively implement test flow alignment. Your team will also collaborate and leverage engineering resources & equipment from PE Dispo Alignment, Silicon Strategy and Global Product and DFT counterparts throughout the phases of Test alignment. Your team will have expert capability on the Probe, Burn and Automated Test Equipment (ATE) code and testing techniques used to validate and ensure device performance. In this role, your additional responsibilities include mentorship of engineers to acquire an in-depth understanding of the details of general device functionality specific to semiconductor memory products, as well as understanding schematics and signal integrity.Responsibilities And Tasks- Leading a team to accomplish the following:
- Drive Global Test Alignment efforts across DRAM & Emerging Memory portfolio
- Drive data collection and analysis to support fanning-in and fanning-out of Best-Known Method (BKM) coverage across DRAM technologies
- Consolidate and document all alignment activity and broadcast of changes in regular cadence
- Execution of tactical activity derived from BKM Test Alignment strategy
- Collaborate with manufacturing sites DFT/Test Development to implement cross-technology alignment
- Collaborate with Silicon Strategy & Alignment team on Time-zero design driven alignment
- Collaborate with cross-functional teams (Yield Enhancement/Global Quality/Product Quality Assurance/Process Engineering) on Manufacturing Yield & Quality driven alignment
- Act as point of communication for DEG PE DFT Alignment updates on test flow alignment status to cross-functional teams across the company
- Excellent problem-solving and analytical skills
- The ability to work in a team environment
- Drive continuous improvement and relentlessly pursue efficiency and results
- Effective communication skills in written and spoken English
- Self-motivation and passionate about technical and people leadership, and drive toward learning and development
- Good multitasking and organizational skills
- Technical leadership experience preferred and People leadership experience a plus
- Experience working with cross-functional teams across multiple sites
- 3+ years of experience with DRAM capability on Probe, Burn, or ATE code and testing techniques and failure analysis with automated test equipment
- Background with Micron Test Flow and Patterns
- DRAM Process Experience
- Circuit Level Debug Experience
- Circuit Simulation using Cadence or other industry standard tools
- Course work in VLSI, semiconductor process, and C/C++ is a plus.
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Plazo: 20-12-2024
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