Posición: Director

Tipo de empleo: Full-time

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Contenido de trabajo

The successful candidate shall possess the capability to design and analyze high speed, high performance analog, and mixed-signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall support team building, supervise the technical activities, and collaborate with remote teams in HQ. She or he shall have solid experience in analog and mixed-design verification and ensuring corner cases are tested.

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth.

If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!

Engaging in the high-speed, high-performance analog and mixed signal circuit design. You have the chance to create the technical differentiation for Infinera to hold the market leadership. We, together as a team, will revolutionize the era of efficient high-speed transmission by building the cutting-edge circuitry.

Essential Functions and Key Responsibilities:

  • Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES.
  • Guide layout floor plan block and top level to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary.
  • Be meticulous about all design and layout details to ensure all the work under supervision meets the quality standard.
  • Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure that the design meets or exceeds target goals.
  • Need to comply with the team’s design methodologies, ensuring that all documentation is completed, and release flows followed.
  • Need to provide technical supervision to team members, and monitor project schedules and come up with mitigation plans to ensure schedule success.

Mandatory Knowledge/Skills/Abilities:

  • Must have a proven tracking record of designing high speed circuits, including but not limited to ADC, DAC, SERDES, and PLL, in deep submicron CMOS FinFET technologies, and taking the IP designs into production.
  • Must have a decent understanding in CMOS analog/mixed-signal design methodologies and circuit analysis.
  • Must have a good understanding of device physics and the impacts of layout effects.
  • Must have a tracking record of managing a team of 5 or more design and layout engineers at least two years.
  • Collaborative with other local or remote team members in a fast-paced professional environment.
  • Has experience in project management and is willing to handle logistics.

Preferred Knowledge/Skill/Abilities:

  • Fluent in verbal and written communications.
  • Capable of coaching and mentoring circuit designers and layout engineers.
  • Independently solve difficult design challenges, and debug silicon.
  • Work with the team in HQ to promote good design practices and methodologies and boost team’s productivity.
  • Have experience with debug of mixed-signal IP on large digital chips.
  • Self-motivated and detail oriented.
  • Has good interpersonal skills.

Education and Experience Requirements:

  • M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 10+ years’ experience
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Plazo: 20-12-2024

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