Posición: Entry level

Tipo de empleo: Full-time

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Contenido de trabajo

Job Details:

Job Description:

External Manufacturing Production (EMP) Team, integral to Intel’s IDM 2.0 Vision, is focused on High Volume Manufacturing (HVM) of Intel products through collaboration with third-party Foundry and Outsourced Semiconductor Assembly and Test suppliers. We seek a DFX (Design for Excellence) CAD Flow and Methodology Engineer to join our Manufacturing Quality Enhancement - Diagnostics and Systems Development (DSD) team. This role offers exceptional growth opportunities, providing broad exposure to the entire semiconductor product lifecycle, from initial definition to HVM. You’ll engage with advanced design, production, and technology processes, collaborating with stakeholders across the company and our supplier ecosystem.

Key Responsibilities:

  • Develop and optimize tools, methods, and flows for Design for Test (DFT), diagnostics, and yield analysis.
  • Manage EMP’s CAD infrastructure and computational resources for HVM Diagnostics, supporting production across EMP product lines
  • Collaborate with external vendors and internal teams to establish standard industry practices for diagnostics and yield analysis.
  • Maintain relationships with Electronic Design Automation (EDA) vendors to access the latest tools and methodologies.
  • Facilitate knowledge transfer to ensure Yield Management and Failure Analysis team members are updated with the latest methodologies and tools.
  • Define and monitor DFX quality metrics (coverage, test cost, and debuggability) from development to production ramp-up.
  • Work closely with Design and New Product Introduction (NPI) teams to ensure diagnostic readiness for new products.
  • Support yield, test, assembly, packaging, process, and foundry teams post-NPI for HVM yield improvement.
As a successful candidate, you must possess:

  • Strong experience with SOC / IP DFT control architectures (e.g., JTAG, IJTAG, IEEE1500).
  • Excellent communication skills, willing to drive clarity among diverse stakeholders.
  • Team-oriented, flexible, and eager to contribute to team success.
  • Eagerness to learn and adapt to various DFX flows and methodologies.
  • Strong problem-solving and task force management skills.
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Ph.D. with 2+ years or MSEE with 7+ years or BSEE with 10+ years of relevant experience in DFT, Scan Diagnostics, Yield Analysis, and EDA tools.
Preferred Qualifications:

  • Experience in Custom and/or ASIC circuit design.
  • Basic understanding of device physics, silicon foundry processes, and semiconductor yield and diagnostics analysis.
  • Proficiency in Python, TCL, C-Shell, Make, and PERL scripting.
  • Experience with Siemens’s Test and Yield Analysis tools or similar.
  • Experience with Synopsys’s Yield Analysis tools or similar.
  • Proficiency in English, both spoken and written.
Job Type:

Experienced Hire

Shift:

Shift 1 (Taiwan)

Primary Location:

Taiwan, Hsinchu

Additional Locations:

Malaysia, Penang, South Korea, Seoul, Taiwan, Taipei

Business group:

Intel’s Sales and Marketing (SMG) organization works with global customers and partners to solve critical business problems with Intel based technology solutions. SMG works across business units to amplify the customer voice and deliver solutions that accelerate their business. We work across numerous industries, including retail, enterprise and government, cloud services and healthcare as examples. The operations team focuses on forecasting, driving alignment with factory production and delivering efficiency tools and our marketing capability drives demand and localized marketing in locations around the globe. Our sales force navigates a complex partner and customer ecosystem while shaping product roadmaps, driving value for our customers, and collaborating to harness emerging technology trends to deliver comprehensive solutions.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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Plazo: 20-12-2024

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