Design Engineer

Contenido de trabajo

Seeking a design engineer with 3 to 8 years of experience. Reporting to the Manager of HW Engineering ASIC & FPGA you will provide innovative solutions to our FPGA design effort. This is a unique opportunity to create first to market chip designs and to contribute to the future of ATE instruments within COHU Semiconductor Test Group products.

Essential Duties and Responsibilities:

This role provides detailed technical engineering in concert with the experienced staff of the ASIC and FPGA group. This includes the implementation of the fpga devices which provide support for the functions of the instrument and in many cases the major portion of the instrument’s capabilities. These features include:

• Pattern generation with opcode driven vector generation for digital pin channels which drive signals to the device under test.

• DSP functionality in digitizers for analog waveform capture and analysis.

• DIMM Memory access and pattern sequencing for AWG and DIG functions.

• Power supply and analog channel instruments utilize fpgas for switch and relay control, sequencing and measurements.

• All instruments also feature support for PCIe connectivity to access their functions.

Work activities include:

• IC design using state-of-the-art Altera and Xilinx FPGA devices, including synthesis, place and route, timing constraints and closure.

• RTL module design, simulation test bench design and verification.

• IC characterization and lab bring-up.

• Designs are mainly targeted to FPGA devices but may also involve some ASIC work.

• Generation of technical documentation and reports.

• Working with the software and board design engineers to ensure proper integration of the IC into an overall instrument.

Qualifications:

• BSEE, BCE, MSEE, PHD

• Minimum 3 years of work experience designing complex digital RTL modules and FPGAs is required.

• Module RTL design, test bench development and module verification work experience is required

• Xilinx (Vivado) and/or Altera (Quartus Prime) tools work experience is required

• Verilog language work experience is required.

• Working knowledge of Python is desired.

• English language proficiency is required

• Ability to use computer applications, including data analysis tools, word processing, spreadsheet, and presentation software.

• Ability to work independently or as part of a team and follow through on assignments with minimal supervision.

• Ability to complete assignments with attention to detail and high degree of accuracy.