CMOS MOL/BEOL Foundry Interface Engineer, Silicon

Contenido de trabajo

Google welcomes people with disabilities.

Minimum qualifications:

• 3 years of experience in MOL/BEOL process development in sub-10nm semiconductor processes
• Experience with MOL/BEOL process window, yield impact characterization through structure design/verification, including implementation of RC device test structure layout/experimental measurements
• Experience with trade-off decisions for interconnect stacks (design rules/process integration) impacting product PPA and yield ramp
  
  

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering or Physics, or other related field with emphasis on semiconductor materials and device physics
• Experience with Raphael, Star-RCXT, and XRC
• Understanding of Simulation Program with Integrated Circuit Emphasis (SPICE) modeling
• Understanding of material properties, far backend bumping, chip-package interaction, and reliability
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As the Complementary Metal–Oxide–Semiconductor (CMOS) device and foundry interface engineer, you will responsible for driving CMOS foundry partners and tracking design kits and design collaterals development, assess technology risks, and work on test chips. You will support IP and chip design and implementation teams on planning and performing CMOS scaling and power/performance analysis (PPA), and producing technology roadmap benchmarks.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Work with foundry partners to define, develop, and productize Back End Of the Line (BEOL) and Middle Of Line (MOL) stack in advanced CMOS technology platform meeting Google Product requirements.
• Work with internal design teams to determine the metal stack to meet product speed, power, IR drop, and routing tracks.
• Evaluate MOL architecture impact on design IP scaling and performance. Understand foundry process integration scheme and design rules for Power/Performance/Area, Product yield and fast manufacturing ramp.
• Lead foundry interactions on metal stack targeting, RC modeling, and verifying key foundry deliverables such as RC model tech files.
• Lead model to silicon verification through multiple test vehicles, and help bring products to market with entitlement yield.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .