Job type: Full-time

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Job content

Dear All, we’re hiring.

You’re very welcomed to join us to create a new world!

- Competitive monthly based on your capability

- Guaranteed 14 months yearly

- Extra bonus depends on performance

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Job description

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EDA Engineer, C++, Simulation Technologies

Responsible for designing, developing, and debugging on verification EDA tool for ESL/RTL SoC design.

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Qualification

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- Master or PhD in Computer Science.

- 5+ years experience in EDA tools development;

- TOEIC Blue/Gold (730+)

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Key Capabilities

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- Proven C++ and SW engineering skills;

- Proven data structures and algorithm knowledge;

- Proven SoC modeling and simulation knowledge;

- Familiar with revision control tools (SVN/Subversion);

- Familiar with Linux working environment (as a user, advanced commands);

- Analytic thinking and SW debugging skills;

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Preferred Experience

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- Hardware description language: SystemVerilog/Verilog

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Deadline: 20-12-2024

Click to apply for free candidate

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